FPGA implementation of synchronous section-carry based carry look-ahead adders

It is common knowledge that carry look-ahead adders constitute a high-speed method of performing binary addition in logarithmic time. As an improvement, in this paper, FPGA based realization of high-speed carry look-ahead adders based on the concept of section-carry is discussed. Three kinds of carry look-ahead adder architectures viz. Type 1, Type 2, Mixed are presented. In comparison with conventional carry look-ahead adders of sizes 16, 32 and 64-bits, the proposed section-carry based carry look-ahead adders report improvements in speed of 14.9%, 12.1% and 13% for Type 1, Type 2 and Mixed topologies respectively, for simulations targeting a 90nm FPGA device.