Improved linearity standard cell based flash ADC with DBNS encoding scheme

Author

Palsodkar, Prasanna ; More, Sagar ; Dakhole, P.K.

Author_Institution

Dept. of Electron. Eng., Yeshwantrao Chavan Coll. of Enginering, Nagpur, India

fYear

2014

fDate

6-8 March 2014

Firstpage

1

Lastpage

5

Abstract

In this paper three different designs are discussed in term of their linearity. Proposed ADC consists of a linearity improved comparator scheme consist of CMOS standard cells (NAND, NOR) in place of Inverter based comparators which eliminate need of feature size variation. Instead of using traditional encoding strategy; Double Base Number System based encoder assembled with ADC to improve speed. This assembly can process arithmetic operations fast due to its multidimensional logarithmic number feature.

Keywords

CMOS digital integrated circuits; NAND circuits; NOR circuits; analogue-digital conversion; comparators (circuits); digital arithmetic; logic design; CMOS standard cells; DBNS encoding scheme; NAND; NOR; arithmetic operations; double base number system based encoder; encoding strategy; inverter based comparators; linearity improved comparator scheme; linearity standard cell based flash ADC; multidimensional logarithmic number feature; CMOS integrated circuits; Digital signal processing; Inverters; Linearity; Logic gates; Threshold voltage; ADC; Comparator; DBNS; Flash; TIQ; linearity;

fLanguage

English

Publisher

ieee

Conference_Titel

Devices, Circuits and Systems (ICDCS), 2014 2nd International Conference on

Conference_Location

Combiatore

Type

conf

DOI

10.1109/ICDCSyst.2014.6926158

Filename

6926158