FPGA based realization of OFDM transceiver system for Software Defined Radio

This paper describes the design and implementation of OFDM transmitter and Receiver in Partial Reconfigurable (PA) FPGA for Software Defined Radio (SDR) system. PR blocks inside FPGA helps in reducing the complexity in SDR system design, overall power and area consumption. The OFDM transceiver is designed with scalable FFT/IFFT- and three types of modulations. An intelligent receiver design is being used, which identifies the type of modulation employed based on the features present in receiving signal and reprograms demodulation circuit at run time without changing much in other baseband processing modules. Further, A unique technique of Peak to Average Power Ratio (PAPR) reduction is being implemented.