Design of area efficient Reed Solomon decoder

In this paper, a Reed Solomon (255, 239) error correction code is modeled to detect and correct the data transmitted in a noisy channel. Reed Solomon (RS) codes are a very powerful in correcting random error and bursty error that is used to ensure the errors correction in digital communication systems. RS decoder modeling using Verilog Language (suitable to be implemented on a Field Programmable logic Array (FPGA). The arithmetic operations which are used in RS code are Galois Fields (GF) addition and multiplication. This paper presents: i) RS encoder modeled using MATLAB with data encoded in the noisy channel for functional verification. ii) RS decoder modeled in Verilog Language to recover the erroneous data. The Verilog modeled RS (255, 239) decoder has the capability of 8 symbol-errors detection and correction.