Designing energy efficient logic gates with Hetero junction Tunnel fets at 20nm

This paper presents the design insights and benchmarking of 20nm Hetero-junction Tunnel transistor (HTFET) as steep slope device for designing energy efficient logic gates. 20nm Si FinFET technology has been used for benchmarking HTFET circuit performance. The HTFET logic topologies have improved robustness and energy efficiency over Si FinFET topology, particularly for small supply voltages. This work further explores the analysis of HTFET based cascaded chain of inverters to drive a large capacitive load. It has been demonstrated that HTFET based circuit design opens path for energy efficient logic design not achievable with CMOS technology at small supply voltages.