Low power consumption of sequential circuit of digital ICS

In this paper a new flip flop in the clock distribution network is introduced. Normally in the clock distribution networks a sinusoidal signal is given at the clock port. Here we are using the low swing DCCF by using reduced swing inverters. This flip flop output has to be checked at the two corners by using simulations that has to be extracted from the layout. The LS-DCCF has to be simulated by using the micro wind layout editor which is to be fabricated in the CMOS technology. The LC resonant clocking scheme has to be achieved around 5.8% in power reduction & the area consumption is about 5.7%. This unit has to be fabricated in 90nm CMOS technology. This paper presents low power clock tree by distributing the clock signal at a lower voltages and translating it to a higher voltage at the extreme point. It also avoids unwanted internal node transitions & leakage current problems. The resonant clock distribution network has high power savings compared to conventional square wave clocking. In the proposed paper the reduced swing inverters size has to be reduced and also the power savings has to be increased.