Title :
Layout driven retiming using the coupled edge timing model
Author :
Neumann, Ingmar ; Kunz, Wolfgang
Author_Institution :
Dept. of Electr. Eng. & Inf. Technol., Univ. of Kaiserslautern, Germany
fDate :
7/1/2003 12:00:00 AM
Abstract :
Retiming is a widely investigated technique for performance optimization. It performs powerful modifications on a circuit netlist. However, often it is not clear whether the predicted performance improvement is still valid after placement has been performed. This paper presents a new retiming algorithm using a highly accurate timing model. It takes into account the effect of retiming on capacitive loads of single wires as well as fanout systems. Further, we propose the integration of retiming into a timing-driven standard cell placement environment. Retiming is used as an optimization technique throughout the whole placement process. The experimental results show the benefit of the proposed approach. In comparison with the conventional design flow based on the standard FEAS algorithm, our approach achieved an improvement in cycle time of up to 34% and 17% on the average.
Keywords :
circuit layout CAD; circuit optimisation; delays; high level synthesis; integrated circuit interconnections; integrated circuit layout; timing; accurate timing model; capacitive loads; circuit netlist modifications; coupled edge timing model; fanout systems; interconnect delay; layout driven retiming; logic design; logic synthesis; logic-layout interaction; optimization technique; performance optimization; retiming algorithm; standard cell placement environment; timing-driven placement environment; CMOS technology; Circuit testing; Coupling circuits; Delay; Logic testing; Optimization; Power system modeling; Registers; Semiconductor device modeling; Timing;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2003.814253
