Implementation of optimized high performance 4×4 multiplier using ancient Vedic sutra in 45 nm technology

Author

Kundu, Diptendu Kumar ; Srimani, Supriyo ; Panda, Siddhartha ; Maji, Bansibadan

Author_Institution

Electron. & Telecommun. Dept., Narula Inst. of Technol., Kolkata, India

fYear

2014

fDate

6-8 March 2014

Firstpage

1

Lastpage

6

Abstract

With the enrichment of new technology in the fields of VLSI design and communication there is also a demand of high speed and low area. The aim of this paper is to design a multiplier circuit based on Vedic sutras. The algorithms based on conventional mathematics can be optimized and simplified by using Vedic sutras. In this paper we have given the design up to Multipliers based on Vedic multiplication sutra “Urdhva-Tiryakbhyam” the design of 2×2, 4×4 has been designed in DSCH2 and all the outputs have been given. The layout of those circuits has been also generated by Microwind. The internal circuit diagram of all the blocks has been explained The noise, power have been calculated by T-Spice-13 in 45nm Technology. The hardware has also been implemented in XILINX and tested in Basys™2 Spartan-3E FPGA Board.

Keywords

VLSI; field programmable gate arrays; integrated circuit layout; multiplying circuits; 4×4 multiplier circuit; Basys™2 Spartan-3E FPGA board; DSCH2; Microwind; T-Spice-13; Urdhva-Tiryakbhyam; VLSI design; Vedic multiplication sutra; XILINX; internal circuit diagram; size 45 nm; Adders; Delays; Layout; Logic gates; MOS devices; Noise; Transistors; DSCH2; MICROWIND; T-Spice; Urdhva Tiryakbhyam; XILINX;

fLanguage

English

Publisher

ieee

Conference_Titel

Devices, Circuits and Systems (ICDCS), 2014 2nd International Conference on

Conference_Location

Combiatore

Type

conf

DOI

10.1109/ICDCSyst.2014.6926192

Filename

6926192