FPGA implementation of secure image compression with 2D-DCT using Verilog HDL

Author

Jeevan, B. ; Bhatt, C. Nagesh ; Krishna, C.V. ; Sivani, K.

Author_Institution

Dept. of E&IE, KITS, Warangal, India

fYear

2014

fDate

6-8 March 2014

Firstpage

1

Lastpage

4

Abstract

The Secure Image Compression consists of JPEG encoder in which 2D-DCT (2Dimensional - Discrete Cosine Transform) is used to provide security while compressing the image. In this paper Verilog design and hardware implementation of pipelined 2-D DCT are described. The architecture uses 4327 slices, 7621 LUTs, 25 I/Os of FPGA Spartan3E-XC3S500E and works at an operating frequency of 89.469MHz. The delay of processing each 8*8 block in an image is evaluated to be 9.167ns and pipeline latency is 66 clock cycles.

Keywords

data compression; discrete cosine transforms; field programmable gate arrays; hardware description languages; image coding; security of data; 2D-DCT; 2dimensional-discrete cosine transform; FPGA implementation; JPEG encoder; Verilog HDL; data security; image compression; Computer architecture; Discrete cosine transforms; Field programmable gate arrays; Hardware design languages; Image coding; Quantization (signal); Transform coding; 2D-DCT; JPEG encoder; image compression; image security;

fLanguage

English

Publisher

ieee

Conference_Titel

Devices, Circuits and Systems (ICDCS), 2014 2nd International Conference on

Conference_Location

Combiatore

Type

conf

DOI

10.1109/ICDCSyst.2014.6926210

Filename

6926210