Title :
Hot-electron resistance device processing and design: a review
Author :
Sanchez, Julian J. ; Hsueh, Kelvin K. ; DeMassa, T.A.
Author_Institution :
Intel Corp., Chandler, AZ, USA
Abstract :
Continual reduction of MOS device size to optimize device performance and reduce die cost has led to reliability concerns. These are attributed to the ever increasing generation of hot electrons that accompany device size reduction. Hence, it is essential to thoroughly understand the relationships governing device performance, design, and reliability with respect to processing. Both the degradation rate and generation of hot electrons can be modified through processing and design. By reviewing various aspects of hot-electron resistance processing and fabrication techniques, guidelines are established which will prove useful in the design of a given process to reduce hot-electron degradation.<>
Keywords :
MOS integrated circuits; hot carriers; insulated gate field effect transistors; integrated circuit technology; reliability; reviews; semiconductor technology; MOS device; design guidelines; fabrication techniques; hot-electron degradation; hot-electron resistance processing; reliability; review; Annealing; Capacitors; Degradation; Electron traps; Hydrogen; Interface states; Nitrogen; Oxidation; Process design; Voltage;
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on