Title :
An efficient maximum-redundancy radix-8 SRT division and square-root method
Author :
Hobson, Richard F. ; Fraser, Michael W.
Author_Institution :
Sch. of Comput. Sci., Simon Fraser Univ., Burnaby, BC, Canada
fDate :
1/1/1995 12:00:00 AM
Abstract :
A new approach to integrating hardware multiplication, division, and square-root is presented. We use a fully integrated control path which simultaneously reduces part of the redundant partial-remainder and performs a truncated multiplication of the next quotient or square-root digit by the divisor or square-root value. A separate (parallel) full precision iterative multiplier is used for partial remainder production. Strategic details of a radix-8 implementation are discussed. It is shown that a maximally redundant digit set is a viable choice for high performance in this case
Keywords :
CMOS digital integrated circuits; adders; digital arithmetic; dividing circuits; floating point arithmetic; multiplying circuits; 1.2 mum; CMOS adder cell; CMOS divider; IEEE floating point algorithm; division; integrated control path; maximally redundant digit set; maximum-redundancy radix-8 SRT algorithm; multiplication; parallel iterative multiplier; partial remainder production; redundant partial-remainder; square-root method; table lookup; CMOS technology; Centralized control; Design methodology; Equations; Floating-point arithmetic; Hardware; Iterative algorithms; Production; Silicon; Space technology;
Journal_Title :
Solid-State Circuits, IEEE Journal of
