Design of a CMOS buffered switch for a Gigabit ATM switching network

Author

Mirfakhraei, Nader

Author_Institution

Comput. & Commun. Res. Center, Washington Univ., St. Louis, MO, USA

Volume

30

Issue

1

fYear

1995

fDate

1/1/1995 12:00:00 AM

Firstpage

11

Lastpage

18

Abstract

This paper presents the implementation and design of a gigabit ATM Switch element used in a broadcast ATM switching network supporting 600 Mb/s link rates. The system is designed to operate at the clock speed of 100 MHz. The design of the switch element is developed to fabricate prototype chips using 1.2 μ CMOS VLSI technology. The network is constructed with a 256-port Benes topology and the switch element consists of nine identical data slices, and a global controller. Each data slice uses 48 shared buffers. The controller determines which buffer cells are to be sent to the outputs based on its internal contention resolution process. This process is carried out by an arbitration circuit and the decision is made by a buffer control circuit. The controller also generates grant flow control through the network

Keywords

B-ISDN; CMOS digital integrated circuits; VLSI; asynchronous transfer mode; buffer circuits; packet switching; 1.2 micron; 100 MHz; 600 Mbit/s; B-ISDN; Benes topology; CMOS VLSI technology; CMOS buffered switch; arbitration circuit; broadcast packet switching network; buffer cells; clock speed; gigabit ATM switching network; global controller; grant flow control; internal contention resolution process; shared buffers; switch element; Asynchronous transfer mode; B-ISDN; Broadcasting; CMOS technology; Circuits; Communication switching; Communication system control; Communication system traffic control; Switches; Very large scale integration;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.350200

Filename

350200