Mitigation Techniques for Single-Event-Induced Charge Sharing in a 90-nm Bulk CMOS Process

Author

Amusan, Oluwole A. ; Massengill, Lloyd W. ; Baze, Mark P. ; Bhuva, Bharat L. ; Witulski, Arthur F. ; Black, Jeffrey D. ; Balasubramanian, Anupama ; Casey, Megan C. ; Black, Dolores A. ; Ahlbin, Jonathan R. ; Reed, Robert A. ; McCurdy, Michael W.

Author_Institution

Electr. Eng. & Comput. Sci. Dept., Vanderbilt Univ., Nashville, TN

Volume

9

Issue

2

fYear

2009

fDate

6/1/2009 12:00:00 AM

Firstpage

311

Lastpage

317

Abstract

In this paper, mitigation techniques to reduce the increased SEU cross section associated with charge sharing in a 90-nm dual-interlocked-cell latch are proposed. The increased error cross section is caused by heavy-ion angular strikes depending on the direction of the ion strike, thereby exacerbating charge sharing among multiple circuit nodes. The use of nodal spacing as a mitigation technique shows an order of magnitude decrease on upset cross section as compared to a conventional layout, and the use of guard-rings show no noticeable effect on upset cross section.

Keywords

CMOS integrated circuits; integrated circuit design; ion beam effects; radiation hardening (electronics); SEU cross section; bulk CMOS process; dual-interlocked-cell latch; heavy-ion angular strike direction; mitigation technique; multiple circuit nodes; nodal spacing; single-event-induced charge sharing; size 90 nm; Charge sharing; dual-interlocked-cell (DICE) latch; guard-rings; heavy ion; nodal spacing; single-event (SE) circuit characterization; soft-error cross section;

fLanguage

English

Journal_Title

Device and Materials Reliability, IEEE Transactions on

Publisher

ieee

ISSN

1530-4388

Type

jour

DOI

10.1109/TDMR.2009.2019963

Filename

4812109