Runtime 3-D stacked cache data management for energy minimization of 3-D chip-multiprocessors

In a 3-D processor-memory system, multiple cache dies can be stacked onto multi-core die to reduce latency and power of the on-chip wires connecting the cores and the cache, which finally increases the power efficiency. However, there are two challenging issues. The first is the high power density (resulting from multiple die stacking) that incurs many temperature-related problems including temperature-dependent leakage power. The second is the processor-cache traffic congestions that occur at through-silicon vias (TSVs) shared by multiple stacked caches. In this paper, a runtime cache data mapping is proposed for 3-D stacked L2 caches to minimize the overall energy of 3-D chip multiprocessors (CMPs). The proposed method considers both temperature distribution and memory traffic of 3-D CMPs. Experimental result shows that the proposed method achieves up to 22.88% energy reduction compared to an existing solution which considers only the temperature distribution.