Title :
Designing self-timed devices using the finite automaton model
Author :
Varshavsky, Victor I. ; Marakhovsky, Vyachesiav B. ; Smolensky, Vadim V.
Author_Institution :
Comput. Logic Design Lab., Aizu Univ., Japan
Abstract :
The authors suggest a procedure for designing a self-timed device defined by the finite automaton model. This procedure proves useful when designing these devices using the available synchronous behavior specifications. They illustrate the effectiveness of their procedure by applying it to the design of a stack memory and constant acknowledgement delay counter
Keywords :
finite automata; formal specification; constant acknowledgement delay counter; finite automaton model; self-timed devices; stack memory; synchronous behavior specifications; Art; Automata; Circuits; Delay effects; Design automation; Master-slave; Power system modeling; Power system reliability; Process design; Signal processing;
Journal_Title :
Design & Test of Computers, IEEE
