Title :
Automatic verification of asynchronous circuits
Author :
Lee, Trevor W s ; Greenstreet, Mark R. ; Seger, Carl-Johan
Author_Institution :
British Columbia Univ., Vancouver, BC, Canada
Abstract :
Verifying asynchronous designs is difficult, since design errors may manifest themselves only under rare circumstances. This article describes how to model asynchronous designs as programs in synchronized transitions, a general-purpose hardware description language. The authors show how this representation facilitates rigorous, efficient verification
Keywords :
asynchronous circuits; fault diagnosis; logic testing; asynchronous circuits; automatic verification; design errors; general-purpose hardware description language; synchronized transitions; Asynchronous circuits; Circuit simulation; Delay; Hardware design languages; Latches; Logic; Signal design;
Journal_Title :
Design & Test of Computers, IEEE
