• DocumentCode
    1230962
  • Title

    Full systolic binary multiplier

  • Author

    Arechabala, J. ; Boemo, E.I. ; Meneses, J. ; Moreno, F. ; Barrio, C. Lopez

  • Author_Institution
    Dept. de Igenieria Electron., Univ. Politecnica de Madrid, Spain
  • Volume
    139
  • Issue
    2
  • fYear
    1992
  • fDate
    4/1/1992 12:00:00 AM
  • Firstpage
    188
  • Lastpage
    190
  • Abstract
    Describes the architecture of a binary multiplier that, because of its intrinsic regularity and simplicity, may be extended for any number of bits. It is a modification of the array of full adders scheme, which allows the operation with two´s complement numbers in systolic mode. The design has been validated and implemented in the SOLO 1400 environment, using ES2 standard cells. Laboratory prototypes perform a multiplication every 24 ns. Finally, a preliminary evaluation of a full custom version is presented
  • Keywords
    VLSI; digital arithmetic; multiplying circuits; systolic arrays; ES2 standard cells; SOLO 1400 environment; architecture; intrinsic regularity; prototypes; systolic binary multiplier; systolic mode; two´s complement numbers operation;
  • fLanguage
    English
  • Journal_Title
    Circuits, Devices and Systems, IEE Proceedings G
  • Publisher
    iet
  • ISSN
    0956-3768
  • Type

    jour

  • Filename
    139171
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1230962