Title :
Full systolic binary multiplier
Author :
Arechabala, J. ; Boemo, E.I. ; Meneses, J. ; Moreno, F. ; Barrio, C. Lopez
Author_Institution :
Dept. de Igenieria Electron., Univ. Politecnica de Madrid, Spain
fDate :
4/1/1992 12:00:00 AM
Abstract :
Describes the architecture of a binary multiplier that, because of its intrinsic regularity and simplicity, may be extended for any number of bits. It is a modification of the array of full adders scheme, which allows the operation with two´s complement numbers in systolic mode. The design has been validated and implemented in the SOLO 1400 environment, using ES2 standard cells. Laboratory prototypes perform a multiplication every 24 ns. Finally, a preliminary evaluation of a full custom version is presented
Keywords :
VLSI; digital arithmetic; multiplying circuits; systolic arrays; ES2 standard cells; SOLO 1400 environment; architecture; intrinsic regularity; prototypes; systolic binary multiplier; systolic mode; two´s complement numbers operation;
Journal_Title :
Circuits, Devices and Systems, IEE Proceedings G
