DocumentCode :
123098
Title :
RTL datapath optimization using system-level transformations
Author :
Ghandali, Samaneh ; Alizadeh, Behrooz ; Fujita, Masayuki ; Navabi, Zainalabedin
Author_Institution :
Sch. of Electr. & Comput. Eng., Univ. of Tehran, Tehran, Iran
fYear :
2014
fDate :
3-5 March 2014
Firstpage :
309
Lastpage :
316
Abstract :
This paper describe a system-level approach to improve the area and delay of datapath designs that perform polynomial computations over Z2m, which are used in many applications such as computer graphics and digital signal processing domains. This approach optimizes the implementation of multivariate polynomial systems in terms of the number of arithmetic operations by performing optimization on a system level prior to high-level synthesis. Univariate functional decomposition of polynomial expressions and canonization form over Z2m are used in this method. We use GAUT high-level synthesis tool to generate RTL datapath architectures for the optimized polynomials. Experimental results on a set of benchmark applications with polynomial expressions show that this method outperforms conventional methods in terms of the area of the sequential datapath architectures in speed optimization mode with an average improvement of 25.81 %, and the required clock cycles in two modes of speed optimization and area optimization, with an average improvement of 23.48% and 38.24%, respectively.
Keywords :
circuit optimisation; high level synthesis; polynomials; GAUT high-level synthesis tool; RTL datapath architectures; RTL datapath optimization; Z2m; area optimization; arithmetic operations; clock cycles; computer graphics; datapath designs; digital signal processing domains; multivariate polynomial systems; optimized polynomials; polynomial computations; polynomial expressions; register transfer level; sequential datapath architectures; speed optimization mode; system-level transformations; univariate functional decomposition; Clocks; Complexity theory; Computer architecture; Optimization methods; Polynomials; Registers; High-level synthesis; canonization form; polynomial datapath; register transfer level (RTL); system-level transformations; univariate functional decomposition;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Quality Electronic Design (ISQED), 2014 15th International Symposium on
Conference_Location :
Santa Clara, CA
Print_ISBN :
978-1-4799-3945-9
Type :
conf
DOI :
10.1109/ISQED.2014.6783341
Filename :
6783341
Link To Document :
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