DocumentCode
1231005
Title
DIRECS: system design of a 100 Mbit/s digital receiver
Author
Ressen, O. Joe ; Oerder, M. ; Serra, R. ; Meyr, H.
Author_Institution
Aachen Univ. of Technol., Germany
Volume
139
Issue
2
fYear
1992
fDate
4/1/1992 12:00:00 AM
Firstpage
222
Lastpage
230
Abstract
The advances in VLSI technology have made the digital implementation of data receivers feasible at very high data rates. Aspects of the design of a chip set representing a 100 Mbit/s digital receiver for coded 8-PSK modulation are described. The receiver is discussed as an example of complex system design and finally implementation aspects are presented. Special emphasis is given to design methodology, trade-off optimisation and performance results. Attention is paid to the structural and algorithmic design as an integral part of the implementation process to obtain an efficient solution
Keywords
CMOS integrated circuits; VLSI; digital communication systems; digital integrated circuits; phase shift keying; 100 Mbit/s; 100 Mbit/s digital receiver; CMOS; DIRECS; VLSI; algorithmic design; chip set design; coded 8-PSK modulation; complex system design; data receivers; design methodology; digital implementation; digital receiver chip set; high data rates; implementation aspects; implementation process; performance; system design; trade-off optimisation;
fLanguage
English
Journal_Title
Circuits, Devices and Systems, IEE Proceedings G
Publisher
iet
ISSN
0956-3768
Type
jour
Filename
139176
Link To Document