Design of an analogue subthreshold multiplier suitable for implementing an artificial neural network

Author

Walke, R.L. ; Quigley, S.F. ; Webb, P.W.

Volume

139

Issue

2

fYear

1992

fDate

4/1/1992 12:00:00 AM

Firstpage

261

Lastpage

264

Abstract

Describes work undertaken as a final-year undergraduate project and considers the design of an analogue VLSI implementation of the multi-layer perceptron artificial neural network. The network is principally composed of multipliers, and therefore the design effort concentrated on the development of a space-efficient multiplier. The circuit exploits the subthreshold region of operation of a MOSFET and it was necessary to examine in detail the modelling of this region of operation. In the course of the work, design tools made available under the ECAD initiative were used; in particular, the circuit simulator HSPICE was used for parameter extraction, in an unconventional way, to great advantage

Keywords

MOS integrated circuits; VLSI; computerised signal processing; linear integrated circuits; multiplying circuits; neural nets; ECAD initiative; MOSFET; analogue VLSI implementation; analogue subthreshold multiplier; artificial neural network; circuit simulator HSPICE; design tools; electronic CAD; modelling; multi-layer perceptron; multi-layer perceptron network; multipliers; parameter extraction; space-efficient multiplier; subthreshold region; undergraduate project;

fLanguage

English

Journal_Title

Circuits, Devices and Systems, IEE Proceedings G

Publisher

iet

ISSN

0956-3768

Type

jour

Filename

139183