DocumentCode
1231080
Title
Skew-free clock distribution for standard-cell VLSI designs
Author
Blair, G.M.
Author_Institution
Dept. of Electr. Eng., Edinburgh Univ., UK
Volume
139
Issue
2
fYear
1992
fDate
4/1/1992 12:00:00 AM
Firstpage
265
Lastpage
267
Abstract
The control of skew in globally distributed signals is essential to the safe design of VLSI. The author describes a novel technique using Cadence EDGE software, for the creation of a skew-free distribution network in standard-cell designs which is achieved after initial placement by modification of the netlist and insertion of buffers whose drive strength is finally determined alter the component is completely routed
Keywords
VLSI; buffer circuits; cellular arrays; clocks; Cadence EDGE software; buffer insertion; globally distributed signals; netlist modification; optimal buffering; skew control; skew-free distribution network; skewfree clock distribution; standard-cell VLSI designs; standard-cell designs; variable sized buffers;
fLanguage
English
Journal_Title
Circuits, Devices and Systems, IEE Proceedings G
Publisher
iet
ISSN
0956-3768
Type
jour
Filename
139184
Link To Document