DocumentCode
123128
Title
Experimental validation of minimum operating-voltage-estimation for low supply voltage circuits
Author
Sato, Takao ; Kawashima, Junya ; Tsutsui, H. ; Ochi, Hiroshi
Author_Institution
Grad. Sch. of Inf., Kyoto Univ., Kyoto, Japan
fYear
2014
fDate
3-5 March 2014
Firstpage
428
Lastpage
433
Abstract
Sub- and near-threshold circuits have been attracting growing interests because they are suitable for realizing extremely low power and low energy circuits. The estimation of the minimum operating voltage (VDDmin), under which the circuit does not function correctly, is one of the most important issues in their design. In this paper, the distribution of VDDmin is explored through simulations and measurements. Lognormal model-approximation and a quick VDDmin estimation method are validated by the measurements of 124k FFs. Assuming that the VDDmin of a circuit is limited by that of the FFs, VDDmin distribution for any circuits can be efficiently estimated. The measurements of 192 DCT circuits show that the estimation matches with silicon data very well within 10 mV error.
Keywords
CMOS integrated circuits; integrated circuit design; large scale integration; low-power electronics; CMOS process; DCT circuit measurements; LSIs; flip-flop; lognormal model-approximation; low energy circuits; low power circuit; low supply voltage circuits; minimum operating-voltage-estimation; near-threshold circuits; silicon data; sub-threshold circuits; voltage 10 mV; Clocks; Discrete cosine transforms; Estimation; MOSFET; Semiconductor device measurement; Voltage measurement; Subthreshold circuit; low power design; minimum operating voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Quality Electronic Design (ISQED), 2014 15th International Symposium on
Conference_Location
Santa Clara, CA
Print_ISBN
978-1-4799-3945-9
Type
conf
DOI
10.1109/ISQED.2014.6783356
Filename
6783356
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