DocumentCode
1231378
Title
Erratum to “Simulation Study on the Effect of Multiple Node Charge Collection on Error Cross-Section in CMOS Sequential Logic”
Volume
56
Issue
2
fYear
2009
fDate
4/1/2009 12:00:00 AM
Firstpage
529
Lastpage
530
Abstract
In the above titled paper (ibid., vol. 55, no. 6, pp. 3136-3140, Dec 08), Figs. 1, 2, 4, 5, 7, and 8 were incorrectly published. The correct figures, with their corresponding captions, are presented here.
Keywords
Arithmetic; Circuit simulation; Combinational circuits; Frequency; Logic devices;
fLanguage
English
Journal_Title
Nuclear Science, IEEE Transactions on
Publisher
ieee
ISSN
0018-9499
Type
jour
DOI
10.1109/TNS.2009.2019475
Filename
4812279
Link To Document