Fine grained wearout sensing using metastability resolution time

Reliability concerns due to Negative Bias Temperature Instability (NBTI) and Positive Bias Temperature Instability (PBTI) are increasing in nanometer CMOS memory and digital logic. Conventional chip lifetime enhancement techniques rely on run-time wearout sensors to detect device threshold voltage (V_th) shift. In this work, we present a novel wearout sensing technique using metastability resolution time. The circuit consists of a reference inverter and age-tracking inverter cross-coupled to form a metastable cell. The resolution time of this cell is impacted by temporal V_th shift in the tracking devices. The tracking devices are sized relatively large compared to reference inverter to minimize impact of process induced V_th offset. The resolution time measurement is performed in two stages using a ring oscillator based Time to Digital Converter (TDC). The first stage of measurement establishes a reference precision during run time. In the second stage, the actual resolution time is measured relative to the reference. This alleviates impact of process variation and measurement temperature. Implementation and simulation in 32nm Predictive Technology Model indicate a lightweight sensor with estimated area of ~105μm² and tracking power of 239nW. The resolution time of the circuit tracks V_th shift due to both NBTI and PBTI. A worst case measurement error at +/-3σ V_th offset is 9.3% of ΔV_th. A nominal measurement time of ~1ns provides accurate estimate of V_th shift without allowing recovery time for tracking devices.