DocumentCode
123145
Title
Methodology to optimize critical node separation in hardened flip-flops
Author
Shambhulingaiah, Sandeep ; Chellappa, Srivatsan ; Kumar, Sudhakar ; Clark, Lawrence T.
Author_Institution
Sch. of Electr., Comput. & Energy Eng., Arizona State Univ., Tempe, AZ, USA
fYear
2014
fDate
3-5 March 2014
Firstpage
486
Lastpage
493
Abstract
Radiation hardening is a requirement for microelectronic circuits used in aerospace applications as they are prone to radiation induced upsets from high altitude neutrons and ions. The most common method to harden VLSI circuits is to use hardened flip-flops (FFs). The design of these FFs is made more difficult with increasing multi-node charge collection (MNCC) in advanced scaled fabrication processes, which requires that charge storage and other sensitive nodes be separated so that one impinging radiation particle does not affect redundant nodes simultaneously. In this paper we describe a correct by construction design methodology to determine a-priori which hardened FF nodes must be separated, as well as a general interleaving scheme to achieve this separation. We apply the methodology to radiation hardened flip-flops and demonstrate optimal circuit physical organization for protection against multi-node charge collection.
Keywords
VLSI; flip-flops; integrated circuit design; radiation hardening (electronics); FF nodes; MNCC; VLSI circuits; aerospace applications; charge storage; construction design methodology; critical node separation optimization; general interleaving scheme; high altitude ions; high altitude neutrons; impinging radiation particle; microelectronic circuits; multinode charge collection; optimal circuit physical organization; radiation hardened flip-flops; radiation induced upsets; sensitive nodes; Clocks; Delays; Flip-flops; Integrated circuit modeling; Layout; Radiation hardening (electronics); Random access memory; Flip-flop (FF); Multi-Bit Upset (MBU); Radiation Hardening by Design (RHBD); Single Event Effects (SEE);
fLanguage
English
Publisher
ieee
Conference_Titel
Quality Electronic Design (ISQED), 2014 15th International Symposium on
Conference_Location
Santa Clara, CA
Print_ISBN
978-1-4799-3945-9
Type
conf
DOI
10.1109/ISQED.2014.6783364
Filename
6783364
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