Title :
Asymmetric aging of clock networks in power efficient designs
Author :
Arasu, S. ; Nourani, M. ; Cano, Frank ; Carulli, John M. ; Reddy, Veerababu
Author_Institution :
Univ. of Texas at Dallas Richardson, Dallas, TX, USA
Abstract :
Circuit aging due to Bias Temperature Instability (BTI) has become one of the major reliability concerns in digital integrated circuits. In this paper, we analyze the impact of asymmetrical aging due to BTI in the clock tree segments of power efficient designs. The non-uniform aging of launch and capture clock segments not only could violate the setup timing but also could result in gross hold violations. Aging in clock networks also results in pulse width compression which impacts the half-cycle paths´ timing adversely. We show that the conventional static timing analysis (STA) have limitations in detecting these violations and; thus propose a Static Asymmetric Aging Analysis (S3A) algorithm. The S3A is based on the Asymmetric Aging model that is developed and validated using 45nm test-chip data and reliability simulations.
Keywords :
ageing; clocks; integrated circuit design; integrated circuit reliability; BTI; S3A algorithm; STA; bias temperature instability; clock networks; clock tree segments; digital integrated circuits; half-cycle paths timing; nonuniform aging; power efficient designs; pulse width compression; reliability simulations; setup timing; static asymmetric aging analysis algorithm; static timing analysis; test-chip data; Aging; Clocks; Degradation; Logic gates; Mercury (metals); Stress; Timing; Asymmetric Aging; Bias Temperature Instability; Clock Network Aging; Setup/Hold Timing Violations; Static Timing Analysis;
Conference_Titel :
Quality Electronic Design (ISQED), 2014 15th International Symposium on
Conference_Location :
Santa Clara, CA
Print_ISBN :
978-1-4799-3945-9
DOI :
10.1109/ISQED.2014.6783365
