Asymmetric aging of clock networks in power efficient designs

Circuit aging due to Bias Temperature Instability (BTI) has become one of the major reliability concerns in digital integrated circuits. In this paper, we analyze the impact of asymmetrical aging due to BTI in the clock tree segments of power efficient designs. The non-uniform aging of launch and capture clock segments not only could violate the setup timing but also could result in gross hold violations. Aging in clock networks also results in pulse width compression which impacts the half-cycle paths´ timing adversely. We show that the conventional static timing analysis (STA) have limitations in detecting these violations and; thus propose a Static Asymmetric Aging Analysis (S3A) algorithm. The S3A is based on the Asymmetric Aging model that is developed and validated using 45nm test-chip data and reliability simulations.