Title :
TASSER: A temperature-aware statistical soft-error-rate analysis framework for combinational circuits
Author :
Hsueh, Sung S.-Y ; Huang, Ryan H.-M ; Wen, Charles H.-P
Author_Institution :
Dept. of Electr. & Comput. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
Soft error has become one of the most critical reliability issues for nano-scaled CMOS designs. Many previous works discovered that the pulse width due to a particle strike on the device increases with temperature, but its system-level effect has not yet been investigated with statistical soft-error-rate (SER). Therefore, in this paper, a combinational circuit (c17 from ISCAS´85) using a 45nm CMOS technology is f rst observed under different temperatures for SER. As a result, a SER increase (2.16X more) is found on c17 as the ambient temperature elevates from 25°C to 125°C. Second, along with growing design complexity, the operational temperatures of gates are distributed in a wide range and much higher than the ambient temperature in reality. Therefore, we are motivated to build a temperature-aware SSER analysis framework that integrates statistical cell modeling to consider the ambient temperature (Ta) and the temperature variation (Tv), simultaneously. Experimental result shows that our SSER analysis framework is highly eff cient (with multiple-order speed-ups) and accurate (with only <;4% errors), when compared with Monte-Carlo SPICE simulation.
Keywords :
CMOS logic circuits; combinational circuits; integrated circuit design; integrated circuit modelling; integrated circuit reliability; radiation hardening (electronics); statistical analysis; CMOS technology; Monte-Carlo SPICE simulation; SER increase; TASSER analysis framework; ambient temperature; combinational circuits; design complexity; nanoscaled CMOS design; operational temperatures; particle strike; pulse width; reliability issue; size 45 nm; statistical SER analysis; statistical cell modeling; system-level effect; temperature 25 degC to 125 degC; temperature variation; temperature-aware SSER analysis framework; temperature-aware statistical soft-error-rate analysis framework; Circuit faults; Integrated circuit modeling; Load modeling; Logic gates; TV; Temperature distribution; Transient analysis;
Conference_Titel :
Quality Electronic Design (ISQED), 2014 15th International Symposium on
Conference_Location :
Santa Clara, CA
Print_ISBN :
978-1-4799-3945-9
DOI :
10.1109/ISQED.2014.6783372