DocumentCode :
123167
Title :
Avoiding unnecessary write operations in STT-MRAM for low power implementation
Author :
Bishnoi, Rajendra ; Oboril, Fabian ; Ebrahimi, Mojtaba ; Tahoori, Mehdi B.
Author_Institution :
Dept. of Dependable Nano-Comput., Karlsruhe Inst. of Technol. (KIT), Karlsruhe, Germany
fYear :
2014
fDate :
3-5 March 2014
Firstpage :
548
Lastpage :
553
Abstract :
Spin Transfer Torque (STT) is a promising emerging memory technology because of its various advantages such as non-volatility, high density, virtually infinite endurance, scalability and CMOS compatibility. Despite all these features, high write current is still a challenge for its widespread use. When writing a value that is already stored, a significant current flows through the Magnetic Tunnel Junction (MTJ) cell which is almost the same as that required to flip the stored data. This increases the total power consumption of the memory. To address this issue, we propose a technique which can avoid unnecessary write operations with bit-level granularity. Our technique can save 68.9% of the total write power consumption with a minor area overhead (0.68 %) and only a small timing penalty (1.33 %).
Keywords :
MRAM devices; low-power electronics; magnetic tunnelling; CMOS compatibility; MTJ cell; STT-MRAM; bit-level granularity; low power implementation; magnetic tunnel junction cell; memory technology; nanomagnetic random access memory; spin transfer torque; write operation avoidance; Computer architecture; Magnetic tunneling; Magnetization; Microprocessors; Power demand; Resistance; Timing; STT-MRAM; low power; non-volatile memory; write avoidance;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Quality Electronic Design (ISQED), 2014 15th International Symposium on
Conference_Location :
Santa Clara, CA
Print_ISBN :
978-1-4799-3945-9
Type :
conf
DOI :
10.1109/ISQED.2014.6783375
Filename :
6783375
Link To Document :
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