Optimising a high-speed serial/parallel sum-of-products hardware structure with respect to bus utilisation

A novel high-speed serial/parallel (S/P) sum-of-products (SOP) hardware structure, based on two´s complement number coding, as well as the mathematical framework needed when optimising the hardware structure with respect to bus utilisation is presented. The hardware blocks necessary to obtain a regular and efficient circuit structure are described. The SOP hardware structure basically consists of a modified S/P multiplier, performing inner-product computations, and a novel partitioned accumulator, which can always be designed sufficiently large for any application. Estimations of performance/area-cost ratio show that the proposed SOP hardware structure is superior to conventional S/P multiplication-accumulation hardware in most situations