Assertion-based verification for system-level designs

As design abstraction has now got to its next upper level that is System Level, one of the main challenges in this area is how to verify designs that are modeled at System Level. In this paper, we are presenting an environment for functionally verifying system-level designs using assertions. This environment adapts existing EDA simulation tools, which are mainly used for RTL design and verification, and utilizes them for system level verification. In this environment, designs are modeled in SystemC-TLM 2.0, and assertions are written in SystemVerilog. Design and verification parts are connected together using SystemVerilog DPI mechanism, and designs are verified against system level assertions in the course of simulation.