On the relationship between PSRR and clock feedthrough in SC filters

A novel linearized model for calculating the power supply rejection ratio (PSRR) of switched-capacitor (SC) circuits due to switch charge injection (clock feedthrough) is presented. The inclusion of clock feedthrough accounts for the low-frequency PSRR degradation not modeled by other methods. This is particularly important in high-frequency SC circuits, as is confirmed by simulation and measurement results. The model defines a useful link between transient clock feedthrough analysis and effective coupling capacitor models that are suited for AC analysis. The abstraction of differentiating an injected charge with respect to voltage to get effective coupling capacitors leads to efficient analysis techniques, since clock delays and elaborate device models can be considered once at the outset, and then dispensed with in favor of simpler device elements. This makes the model more suitable for hand calculations and analysis with standard SC simulation packages