Building energy-efficient multi-level cell STT-MRAM based cache through dynamic data-resistance encoding

With attractive advantages like high density and low leakage, Spin-Transfer Torque Magnetoresistive RAM (STT-MRAM) is a promising candidate to replace conventional SRAM technology to build large-size and low-power on-chip caches. Multi-level cell (MLC) STT-MRAM, with a higher density, further improves the on-chip cache capacity for chip multiprocessor (CMP) systems. However, the notorious high write energy impedes the adoption of MLC STT-MRAM. In this paper, we focus on minimizing the energy consumption during MLC STT-MRAM write operations. Based on the strong dependency of write energy on data values, a dynamic encoding technique is proposed to map the most frequently appearing data patterns to the most energy-efficient resistance states at runtime. Our experimental results show that, compared with the existing static data mapping scheme, our technique reduces write energy by 12.4% on average and up to 25.4% for a typical MLC STT-MRAM cache.