On pattern generation for maximizing IR drop

Increase in power density and decrease in supply voltage results in greater power supply current. With scaling, line resistance increases. Together with increase in supply current, this results in ever larger IR drop in supply voltage. IR drop analysis is an important element of power supply network design. Maximizing IR drop is also an important component of manufacturing testing. As a CMOS gate primarily draws current during switching, IR drop maximization problem is akin to finding input pattern pair that maximizes circuit switching taking the drive strengths of the gates and their spatial distribution into consideration. In this paper, we examine IR-drop analysis problem for combinational circuits. The solution to the general problem of maximizing IR drop of a power supply network can be reformulated as a pattern generation problem to maximize IR drop at a specific point on the power supply network, as this analysis can then be applied on a collection of target points determined by load distribution on the grid. The main contributions of this paper are (i) formulation of objective function for pattern generation using the spatial location and strengths of the gates and (ii) expressing the Boolean relationships between gates to use in an Integer Linear Programming solver for solving the pattern generation problem. We further show that by exploiting the conic structure of combinational circuits and the proposed formulation of objective function, the technique is easily applied to larger circuits. The proposed technique was applied to ISCAS-85 benchmark circuits and validated in simulation. Results show that with targeted pattern generation and deterministic approach, we achieve ~25 % moreIR drop over random patterns on an average, while average run-time improves by four orders of magnitude.