Stability Analysis of a Novel Proposed Low Power 10T SRAM Cell for Write Operation

This paper focuses on the analysis of stability of a proposed low power 10T SRAM cell during write operation. In the proposed structure there are two voltage sources, one connected with the bit line and the other connected with the bitbar line for reducing the voltage swing during the switching activity. This reduction in voltage swing causes less dynamic power dissipation during switching activity. Two stack transistors are also connected in the pull-down paths which increase the threshold voltages of the pull down transistors and cause the reduction in sub-threshold leakage current and static power dissipation. In this paper we use the approach of write static noise margin, bit line voltage write margin and word line voltage write margin for analyzing the stability of the proposed SRAM cell. These two extra voltage sources control the voltage swing on the output node and improve the noise margin during the write operation. Simulation has been done in 45nm CMOS technology with 1.0 volt power supply in Microwind 3.1 software. Simulation results have been compared to those of other existing SRAM cells.