DocumentCode
1232839
Title
Enhancement of CMOS performance by process-induced stress
Author
Luo, Yuhao ; Nayak, Deepak K.
Author_Institution
Technol. Dev. Group, Xilinx Inc., San Jose, CA, USA
Volume
18
Issue
1
fYear
2005
Firstpage
63
Lastpage
68
Abstract
A detailed analysis of the process-induced stress during a standard CMOS manufacturing is presented. Dependence of transistor performance on layout is attributed to the combination of stress induced by shallow trench isolation and source/drain (S/D) silicide. Based on the layout sensitivity, the effect of an individual stress component on NMOS and PMOS is identified. The optimization of transistor layout is proposed to improve the CMOS performance.
Keywords
CMOS integrated circuits; MOSFET; integrated circuit layout; internal stresses; isolation technology; CMOS performance enhancement; layout sensitivity; process induced stress; shallow trench isolation; source-drain silicide; standard CMOS manufacturing; transistor layout optimization; transistor performance; CMOS process; Compressive stress; Degradation; MOS devices; MOSFET circuits; Manufacturing processes; Region 2; Silicides; Tensile stress; Testing;
fLanguage
English
Journal_Title
Semiconductor Manufacturing, IEEE Transactions on
Publisher
ieee
ISSN
0894-6507
Type
jour
DOI
10.1109/TSM.2004.841831
Filename
1393046
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