Vector pipelining, chaining, and speed on the IBM 3090 and Cray X-MP

Author

Cheng, Hui

Author_Institution

Dept. of Mech. Eng., Illinois Univ., Chicago, IL, USA

Volume

22

Issue

9

fYear

1989

Firstpage

31

Lastpage

42

Abstract

Vector pipelining and chaining are clarified through the use of timing and pipeline diagrams of the instruction execution process. The technique for evaluating the performance of the concurrent vector operations of vector processors is evaluated by testing two of the most widely used computers with vector facilities: the IBM 3090 and Cray X-MP. On the basis of the testing results analyzed at the assembler level, suggestions are given for machine users and designers about vectorization on these two machines. The ideas presented can be applied to other vector processors. The actual implementations, however, may differ, depending on individual machine architecture.<>

Keywords

parallel architectures; performance evaluation; pipeline processing; Cray X-MP; IBM 3090; assembler level; concurrent vector operations; instruction execution process; machine architecture; performance evaluation; pipeline diagrams; speed; testing; timing diagnosis; vector chaining; vector facilities; vector pipelining; vector processors; Assembly; Concurrent computing; Pipeline processing; Testing; Timing; Vector processors;

fLanguage

English

Journal_Title

Computer

Publisher

ieee

ISSN

0018-9162

Type

jour

DOI

10.1109/2.35212

Filename

35212