DocumentCode :
1233006
Title :
Dynamic load balancing among multiple fabrication lines through estimation of minimum inter-operation time
Author :
Toba, Hiroyasu ; Izumi, Hiroaki ; Hatada, Hirotaka ; Chikushima, Takayuki
Author_Institution :
NEC Electron Devices, NEC Corp., Kanagawa, Japan
Volume :
18
Issue :
1
fYear :
2005
Firstpage :
202
Lastpage :
213
Abstract :
We propose a load balancing method which balances all processing operations of products among multiple semiconductor wafer fabrication lines (fabs) by using predictive scheduling results. Through a simulation experiment we confirmed that the proposed method enabled improved load balancing (compared to conventional methods) among multiple fabrication lines each of which can independently fabricate wafers and has different wafer processing capacity. The load balancing feature effectively reduces the waiting time at each process step and the lead time of all products in multiple fabs. Another promising application of the proposed method is performance evaluation of automated material handling systems (AMHS) in terms of inter-operation time, and we have used the method to evaluate the transportation efficiency of actual fabs.
Keywords :
electronics industry; integrated circuit manufacture; lead time reduction; materials handling; scheduling; semiconductor device manufacture; semiconductor technology; automated material handling systems; dynamic load balancing; inter-operation time; lead time; load balancing method; multiple semiconductor wafer fabrication lines; transportation efficiency; wafer processing capacity; waiting time; Fabrication; Job shop scheduling; Lead time reduction; Load management; Manufacturing; Materials handling; National electric code; Production management; Routing; Transportation;
fLanguage :
English
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on
Publisher :
ieee
ISSN :
0894-6507
Type :
jour
DOI :
10.1109/TSM.2004.840535
Filename :
1393061
Link To Document :
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