Title :
A true single-phase energy-recovery multiplier
Author :
Kim, Suhwan ; Ziesler, Conrad H. ; Papaefthymiou, Marios C.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Univ. of Michigan, Ann Arbor, MI, USA
fDate :
4/1/2003 12:00:00 AM
Abstract :
In this paper, we present the design and experimental evaluation of an 8-bit energy-recovery multiplier with built-in self-test logic and an internal single-phase sinusoidal power-clock generator. Both the multiplier and the built-in self-test have been designed in SCAL-D, a true single-phase adiabatic logic family. Fabricated in a 0.5-/spl mu/m standard n-well CMOS process, the chip has an active area of 0.47 mm/sup 2/. Correct chip operation has been verified for clock rates up to 140 MHz. Moreover, chip dissipation measurements correlate well with HSPICE simulation results. For a selection of biasing conditions that yield correct operation at 140 MHz, total measured average dissipation for the multiplier and the power-clock generator is 250 pJ per operation.
Keywords :
CMOS logic circuits; SPICE; built-in self test; clocks; low-power electronics; multiplying circuits; 0.5 micron; 140 MHz; 250 pJ; 8 bit; CMOS chip; HSPICE simulation; SCAL-D; built-in self-test; energy-recovery multiplier; low-power circuit; power dissipation; power-clock generator; single-phase adiabatic logic; Built-in self-test; CMOS logic circuits; CMOS process; Circuit simulation; Circuit testing; Clocks; Logic design; Power generation; Semiconductor device measurement; Very large scale integration;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2003.810795
