Designing fast on-chip interconnects for deep submicrometer technologies

Author

Hossain, Razak ; Viglione, Fabrizio ; Cavalli, Marco

Author_Institution

STMicroelectron. Inc., San Diego, CA, USA

Volume

11

Issue

2

fYear

2003

fDate

4/1/2003 12:00:00 AM

Firstpage

276

Lastpage

280

Abstract

This paper proposes a solution to the problem of improving the speed of on-chip interconnects, or wire delay, for deep submicron technologies where coupling capacitance dominates the total line capacitance. Simultaneous redundant switching is proposed to reduce interconnect delays. It is shown to reduce delay more than 25% for a 10-mm long interconnect in a 0.12-/spl mu/m CMOS process compared to using shielding and increased spacing. The paper also proposes possible design approaches to reduce the delay in local interconnects.

Keywords

CMOS digital integrated circuits; VLSI; capacitance; delay estimation; integrated circuit interconnections; integrated circuit layout; redundancy; switching; 0.12 micron; 10 mm; capacitive coupling; coupling capacitance; deep submicron technologies; high speed interconnects; interconnect delay reduction; line capacitance; local interconnects; on-chip interconnect design; simultaneous redundant switching; CMOS process; CMOS technology; Capacitance; Capacitors; Delay effects; Delay lines; Paper technology; Repeaters; Switches; Wire;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/TVLSI.2003.810781

Filename

1210507