Low-power register-exchange survivor memory architectures for Viterbi decoders

Register exchange (RE) structures are commonly applied to survivor memory design for Viterbi decoders aiming at high-speed, low-latency requirements. The authors explore low-power RE survivor memory architectures based on the trace-forward concept. When trace-forward units (TFUs) are used to derive decoded outputs instead of pointing to merged states in trace-back applications, we have the freedom of selecting the length of TFUs for obtaining different segmented RE (SRE) structures. Using the inherent properties in the TFU and properly setting the initial values of registers in SRE structures, a significant saving in power dissipation and a reduced number of RE stages can then be achieved. Experimental results exhibit that about 54% savings in power can be obtained using our development compared to conventional RE structures.