DocumentCode
1233533
Title
Parallel implementation of a 4*4-bit multiplier using a modified Booth´s algorithm
Author
Shanbhag, Naresh R. ; Juneja, Pushkal
Author_Institution
Indian Inst. of Technol., New Delhi, India
Volume
23
Issue
4
fYear
1988
Firstpage
1010
Lastpage
1013
Abstract
The design of a 4*4-bit multiplier using the modified Booth´s algorithm in 2- mu m NMOS technology is discussed. The main features of this chip are its 62.5-MHz operating frequency and 31.5-mW power dissipation. The chip occupies an area of 1.37 mm/sup 2/. A novel adder-cum-subtractor circuit was designed to realize the arithmetic processing part.<>
Keywords
field effect integrated circuits; integrated logic circuits; multiplying circuits; parallel processing; 2 micron; 31.5 mW; 4*4-bit multiplier; 62.5 MHz; NMOS technology; adder-cum-subtractor circuit; arithmetic processing; modified Booth´s algorithm; monolithic IC; parallel implementation; power dissipation; Adders; Arithmetic; Clocks; Delay systems; Feedback; Logic; Multiplexing; Registers; Signal generators; Timing;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/4.353
Filename
353
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