DocumentCode
1233635
Title
Charge trapping and dielectric reliability of SiO2-Al2O3 gate stacks with TiN electrodes
Author
Kerber, Andreas ; Cartier, Eduard ; Degraeve, Robin ; Roussel, Philippe J. ; Pantisano, Luigi ; Kauerauf, Thomas ; Groeseneken, Guido ; Maes, Herman E. ; Schwalke, Udo
Volume
50
Issue
5
fYear
2003
fDate
5/1/2003 12:00:00 AM
Firstpage
1261
Lastpage
1269
Abstract
A detailed study on charge trapping and dielectric reliability of SiO2-Al2O3 gate stacks with TiN electrodes has been carried out. Due to the inherent asymmetry of the dual layer stack all electrical properties studied were found to be strongly polarity dependent. The gate current is strongly reduced for injection from the TiN (gate) electrode compared to injection from the n-type Si substrate. For substrate injection, electron trapping occurs in the bulk of the Al2O3 film, whereas for gate injection mainly hole trapping near the Si substrate is observed. Furthermore, no significant interface state generation is evident for substrate injection. In case of gate injection a rapid build up of interface states occurs already at small charge fluence (qinj ∼ 1 mC/cm2). Dielectric reliability is consistent with polarity-dependent defect generation. For gate injection the interfacial layer limits the dielectric reliability and results in low Weibull slopes independent of the Al2O3 thickness. In the case of substrate injection, reliability is limited by the bulk of the Al2O3 layer leading to a strong thickness dependence of the Weibull slope as expected by the percolation model.
Keywords
CMOS integrated circuits; Weibull distribution; aluminium compounds; dielectric thin films; electron traps; hole traps; integrated circuit reliability; interface states; silicon compounds; CMOS devices; SiO2-Al2O3; SiO2-Al2O3 gate stacks; TiN electrodes; Weibull slopes; charge fluence; charge trapping; dielectric reliability; dual layer stack; electrical properties; electron trapping; gate current; gate dielectrics; hole trapping; interface state generation; percolation model; polarity-dependent defect generation; CMOS technology; Charge carrier processes; Dielectric substrates; Electrodes; Electron traps; High-K gate dielectrics; Interface states; Semiconductor device modeling; Semiconductor films; Tin;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/TED.2003.813486
Filename
1210772
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