An ultrathin vertical channel MOSFET for sub-100-nm applications

An ultrathin vertical channel (UTVC) MOSFET with an asymmetric gate-overlapped low-doped drain (LDD) is experimentally demonstrated. In the structure, the UTVC (15 nm) was obtained using the cost-effective solid phase epitaxy, and the boron-doped poly-Si_0.5Ge_0.5 gate was adopted to adjust the threshold voltage. The fabricated NMOSFET offers high-current drive due to the lightly doped (<1×10¹⁵ cm^-3) channel, which suppresses the electron mobility degradation. Moreover, an asymmetric gate-overlapped LDD was used to suppress the offstate leakage current and reduce the source/drain series resistance significantly as compared to the conventional symmetrical LDD. The on-current drive, offstate leakage current, subthreshold slope, and DIBL for the fabricated 50-nm devices are 325 μA/μm, 8×10^-9 μA/μm, 87 mV/V, and 95 mV/dec, respectively.