DocumentCode
1234288
Title
A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy
Author
Kratyuk, Volodymyr ; Hanumolu, Pavan Kumar ; Moon, Un-Ku ; Mayaram, Kartikeya
Author_Institution
Sch. of Electr. Eng. & Comput. Sci., Oregon State Univ., Corvallis, OR
Volume
54
Issue
3
fYear
2007
fDate
3/1/2007 12:00:00 AM
Firstpage
247
Lastpage
251
Abstract
In this brief, a systematic design procedure for a second-order all-digital phase-locked loop (PLL) is proposed. The design procedure is based on the analogy between a type-II second-order analog PLL and an all-digital PLL. The all-digital PLL design inherits the frequency response and stability characteristics of the analog prototype PLL
Keywords
digital filters; digital phase locked loops; oscillators; all-digital phase-locked loops; bilinear transform; charge-pump phase-locked-loop; digital loop filter; digitally controlled oscillator; type-II second-order analog PLL; Bandwidth; Charge pumps; Circuit noise; Clocks; Digital control; Digital filters; Digital integrated circuits; Phase locked loops; Semiconductor device noise; Voltage-controlled oscillators; All-digital phase-locked loop (PLL); bilinear transform; digital loop filter; digitally controlled oscillator;
fLanguage
English
Journal_Title
Circuits and Systems II: Express Briefs, IEEE Transactions on
Publisher
ieee
ISSN
1549-7747
Type
jour
DOI
10.1109/TCSII.2006.889443
Filename
4132962
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