Threshold voltage tuning and suppression of edge effects in narrow channel MOSFETs using surrounding buried side-gate

Author

Gokirmak, A. ; Tiwari, S.

Author_Institution

Sch. of Electr. & Comput. Eng., Cornell Univ., Ithaca, NY

Volume

41

Issue

3

fYear

2005

Firstpage

157

Lastpage

158

Abstract

Scalable narrow channel silicon nMOSFETs, the threshold voltage of which can be tuned, are demonstrated. The devices use a buried polysilicon side-gate utilising silicon nitride (Si₃N₄) shallow trench isolation (STI). The side-gate of this device allows the tuning of the threshold voltage (V_t) in a range of approximately 1.5 V with a sensitivity of 0.75 V/V (deltaV_t/deltaV_side). The biased side-gate also suppresses the leakage currents along the silicon-STI interface below 50 fA. This may allow alternative STI materials for increased process and integration flexibility. Surrounding the buried side-gate structure allows very low-power CMOS with threshold tuning in a bulk structure

Keywords

CMOS integrated circuits; MOSFET; buried layers; elemental semiconductors; isolation technology; leakage currents; low-power electronics; silicon; silicon compounds; 1.5 V; STI materials; Si; Si₃N₄; buried polysilicon side gate structure; edge effect suppression; leakage currents; low power CMOS circuits; narrow channel silicon nMOSFET; silicon nitride shallow trench isolation; silicon-STI interface; threshold voltage tuning;

fLanguage

English

Journal_Title

Electronics Letters

Publisher

iet

ISSN

0013-5194

Type

jour

DOI

10.1049/el:20057152

Filename

1393461