Title :
5.7 GHz low-power variable-gain LNA in 0.18 μm CMOS
Author :
Wang, Y.S. ; Lu, L.-H.
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
A variable-gain low-noise amplifier (LNA) suitable for low-voltage and low-power operation is designed and implemented in a standard 0.18 μm CMOS technology. With a current-reused topology, the common-source gain stages are stacked for minimum power dissipation while achieving high small-signal gain. The fully integrated 5.7 GHz LNA exhibits 16.4 dB gain, 3.5 dB noise figure and 8 dB gain tuning range with good input and output return losses. The LNA consumes 3.2 mW DC power from a supply voltage of 1 V. A gain/power quotient of 5.12 dB/mW is achieved in this work.
Keywords :
CMOS integrated circuits; MMIC amplifiers; S-parameters; circuit tuning; field effect MMIC; integrated circuit design; integrated circuit noise; low-power electronics; 0.18 micron; 1 V; 16.4 dB; 3.2 mW; 3.5 dB; 5.7 GHz; 8 dB; CMOS technology; common source gain; current reused topology; gain tuning range; gain-power quotient; input losses; low-power operation; low-power variable gain LNA; low-power variable gain low noise amplifier; low-voltage operation; minimum power dissipation; noise figure; output return losses; small signal gain;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20057230
