Title :
REDUSA: module generation by automatic elimination of superfluous blocks in regular structures
Author :
Vandeweerd, I. ; Croes, Kris ; Rijnders, L. ; Six, Paul ; De Man, Hugo J.
Author_Institution :
IMEC, Leuven, Belgium
fDate :
9/1/1989 12:00:00 AM
Abstract :
An approach to module generation that does not require the construction of parametrized software procedures is presented. It is a design-by-example method that is based on the following concept: an example module (e.g., a 16-b multiplier) realizes a function between the set of input combinations and the set of output combinations. In many applications, only a subset of input combinations (e.g., 8-b instead of 16-b inputs) is used. The restriction of the module´s function to this subset can be realized by a simpler module. REDUSA constructs this module automatically by a reduction of the example module. This approach offers important advantages in both the construction and verification aspected of module generators
Keywords :
application specific integrated circuits; circuit layout CAD; logic CAD; ASIC; CAD; REDUSA; automatic elimination; design-by-example method; logic design; module generation; regular structures; superfluous blocks; Application software; Arithmetic; Design automation; Design methodology; Logic design; Modular construction; Software debugging; Software libraries; Software maintenance; Software tools;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on