Enhancing random-pattern coverage of programmable logic arrays via masking technique

A testable design of programmable logic arrays (PLAs) with high fault coverage for random test patterns is presented. The proposed design is realized with low area overhead by adding two mask arrays to the AND and OR arrays of the PLA. An experiment was performed to demonstrate the effect of the masking technique. In the experiment, eight large PLAs were modified by adding mask arrays of various sizes; fault simulation with random patterns for modified and unmodified PLAs was then carried out to obtain random-pattern test coverage curves. Fault coverage can be significantly enhanced via the proposed masking technique with very low area overhead