The Design and Analysis of a Fully Integrated Multiplying DLL With Adaptive Current Tuning

Author

Hsiao, Keng-Jan ; Lee, Tai-Cheng

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei

Volume

43

Issue

6

fYear

2008

fDate

6/1/2008 12:00:00 AM

Firstpage

1427

Lastpage

1435

Abstract

A multiplying-DLL-based frequency synthesizer with a fully integrated loop capacitor employs an adaptive current-adjusting loop to generate a low-jitter clock. The nonidealities in the general impedance converter (GIC) which is used as the loop capacitor are thoroughly discussed. Additionally, the discrete-time model for the clock generator with adaptive current tuning is presented and the analysis of the loop stability is provided. The frequency synthesizer occupies an active area of 0.09 mm² in a 0.18-mum CMOS technology and consumes 9 mW from a 1.8-V supply. The measured rms jitter is 3.5 ps for a 229.5-MHz output clock.

Keywords

CMOS integrated circuits; capacitors; circuit tuning; delay lock loops; frequency synthesizers; impedance convertors; jitter; CMOS technology; adaptive current tuning; adaptive current-adjusting loop; clock generator; discrete-time model; frequency synthesizer; fully integrated loop capacitor; fully integrated multiplying DLL design; general impedance converter; loop stability; low-jitter clock; multiplying delay-locked loop; power 9 mW; size 0.18 micron; voltage 1.8 V; Bandwidth; CMOS technology; Capacitance; Capacitors; Clocks; Frequency synthesizers; Impedance; Phase locked loops; Stability analysis; Tuning; Adaptive current tuning; capacitance multiplication; general impedance converter; multiplying DLL;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2008.923737

Filename

4531670