A 40-Gb/s Transimpedance Amplifier in 0.18- $\\mu$ m CMOS Technology

Author

Jin, Jun-De ; Hsu, Shawn S H

Author_Institution

Dept. of Electr. Eng. & Inst. of Electron. Eng., Nat. Tsing Hua Univ., Hsinchu

Volume

43

Issue

6

fYear

2008

fDate

6/1/2008 12:00:00 AM

Firstpage

1449

Lastpage

1457

Abstract

A 40-Gb/s transimpedance amplifier (TIA) is realized in 0.18-mum CMOS technology. From the measured S-parameters, a transimpedance gain of 51 dBOmega and a 3-dB bandwidth up to 30.5 GHz were observed. A bandwidth enhancement technique, pi-type inductor peaking (PIP), is proposed to achieve a bandwidth enhancement ratio (BWER) of 3.31. In addition, the PIP topology used at the input stage decreases the noise current as the operation frequency increases. Under a 1.8 V supply voltage, the TIA consumes 60.1 mW with a chip area of 1.17 X 0.46 mm2. The proposed CMOS TIA presents a gain-bandwidth product per DC power figure of merit (GBP/P_de) of 180.1 GHzOmega/mW.

Keywords

CMOS integrated circuits; MMIC amplifiers; S-parameters; CMOS technology; S-parameters; bandwidth enhancement technique; bit rate 40 Gbit/s; gain 51 dB; gain-bandwidth product; noise current; pi-type inductor peaking; power 60.1 mW; power figure of merit; size 0.18 mum; transimpedance amplifier; voltage 1.8 V; Bandwidth; Broadband amplifiers; CMOS technology; Capacitance; Equivalent circuits; Frequency; Inductors; Optical amplifiers; Semiconductor device noise; Wideband; $pi$-type inductor peaking; Bandwidth enhancement technique; CMOS; gain–bandwidth product; transimpedance amplifier (TIA);

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2008.922735

Filename

4531672

A 40-Gb/s Transimpedance Amplifier in 0.18- m CMOS Technology

Jin, Jun-De ; Hsu, Shawn S H

jour

A 40-Gb/s Transimpedance Amplifier in 0.18- $\\mu$ m CMOS Technology